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LTC1552 Digitally Controlled Synchronous Switching Regulator Controller for Pentium(R) Pro Processor
September 1996
FEATURES
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DESCRIPTION
The LTC(R)1552 is a high power, high efficiency switching regulator controller optimized for 5V or 12V input to 2.1V - 3.5V output applications. It features digitally programmable output voltage, a precision internal reference and an internal feedback system that can provide output regulation of 1% over temperature, load current and line voltage shifts. The LTC1552 uses a synchronous switching architecture with two external N-channel output devices, eliminating the need for a high power, high cost P-channel device. Additionally, it senses the output current across the on resistance of the upper N-channel FET, providing an adjustable current limit without an external low value sense resistor. The LTC1552 free runs at 300kHz, and can be synchronized to a faster external clock if desired. It includes all the inputs and outputs required to implement a power supply conforming to the Intel Pentium Pro Processor VRM 8.0 DC/DC Converter Specification.
, LTC and LT are registered trademarks of Linear Technology Corporation. Pentium is a registered trademark of Intel Corporation.
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Digitally Programmable 2.1V to 3.5V Fixed Output Voltage with 100mV Steps Provides All Features Required by the Intel Pentium (R) Pro Processor VRM 8.0 DC/DC Converter Specification Flags for Power Good, Over Temperature and Over Voltage Fault Output Current Exceeds 14A from a 5V or 12V Supply Dual N-Channel MOSFET Synchronous Drive Excellent Output Regulation: 1% Over Line, Load and Temperature Variations High Efficiency: Over 95% Possible Adjustable Current Limit Without External Sense Resistors Fast Transient Response Available in SSOP-20 Package
APPLICATIONS
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Power Supply for Pentium Pro, SPARC, ALPHA and PA-RISC Microprocessors High Power 5V or 12V/2.1V - 3.5V Regulators
TYPICAL APPLICATION
PVCC = 12V 5.6k 5.6k PWRGD FAULT PENTIUM PRO SYSTEM 4 OT VID0 TO VID3 OUTEN COMP C1 100pF RC 20k CC 0.01F G2 SENSE LTC1552 VCC IMAX PVCC G1 Q1A, Q1B 2 IN PARALLEL 2.1V VOUT 3.5V AT 14A 0.1F 10F RIMAX 1.6k 10F VIN = 5V
IN + 990F
5.6k
0.1F
IFB
SS CSS 0.01F
GND
PGND
0.1F
Q1A, Q1B, Q2 = MOTOROLA MTD20N03HDL
Figure 1. 5V to 2.1V - 3.5V Supply Application
Specifications on this data sheet are preliminary only, and subject to change without notice. Contact the manufacturer before finalizing a design using this part.
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C
3x 330F
LO 2H Q2 18A
+
CO 2310F 7x 330F
LTC1552 * F01
1
LTC1552
ABSOLUTE MAXIMUM RATINGS
(Note 1)
PACKAGE/ORDER INFORMATION
TOP VIEW G2 PVCC PGND GND VCC SENSE IMAX IFB SS 1 2 3 4 5 6 7 8 9 20 G1 19 OUTEN 18 VID0 17 VID1 16 VID2 15 VID3 14 NC 13 PWRGD 12 FAULT 11 OT
Supply Voltage VCC ........................................................................ 7V PVCC .................................................................... 20V Input Voltage IFB ............................................ - 0.3V to PVCC + 0.3V IMAX .......................................................- 0.3V to 13V All Other Inputs .......................... - 0.3V to VCC + 0.3V Digital Output Voltage ................................- 0.3V to 13V Operating Temperature Range ..................... 0C to 70C Storage Temperature Range ................. - 65C to 150C Lead Temperature (Soldering, 10 sec).................. 300C
ORDER PART NUMBER LTC1552CG
COMP 10
G PACKAGE 20-LEAD PLASTIC SSOP TJMAX = 125C, JA = 96C/ W
Consult factory for Industrial and Military grade parts.
ELECTRICAL CHARACTERISTICS
SYMBOL VCC PVCC VFB VOUT VOUT VPWRGD VFAULT ICC IPVCC fOSC GERR gmERR IIMAX ISS ISSIL ISSHIL tSSHIL tPWRGD tPWRBAD tFAULT tOT VOT PARAMETER Supply Voltage Supply Voltage for G1 and G2 Internal Feedback Voltage Output Voltage Output Load Regulation Output Line Regulation Positive Power Good Trip Point Negative Power Good Trip Point FAULT Trip Point Normal Supply Current Shutdown Supply Current Supply Current Internal Oscillator Frequency Error Amplifier Open-Loop DC Gain Error Amplifier Transconductance IMAX Sink Current Soft Start Source Current Maximum Soft Start Sink Current Under Current Limit Soft Start Sink Current Under Hard Current Limit Hard Current Limit Hold Time Power Good Response Time Power Good Response Time FAULT Response Time OT Response Time Over Temperature Trip Point CONDITIONS
VCC = 5V, PVCC = 12V, TA = 25C unless otherwise noted (Note 2).
MIN 4.5 TYP MAX 5.5 18 3 7 5 5 -5 15 700 150 15 1 300 53 1.1 185 - 14 130 65 180 300 100 100 30 2 UNITS V V V % mV mV % % % A A mA A kHz dB mMho A A A mA s s s s s V
q q
(Note 3) Figure 2, % Error wrt Rated Output Voltage Figure 2, IOUT = 0A to 12A (Note 3) Figure 2, VIN = 4.75V to 5.25V (Note 3) Figure 2, % Above Rated Output Voltage Figure 2, % Below Rated Output Voltage Figure 2, % Above Rated Output Voltage Figure 3, OUTEN = VCC (Note 4) Figure 3, OUTEN = 0, VID0, VID1, VID2, VID3 Floating Figure 3, PVCC = 12V, OUTEN = VCC (Note 5) PVCC = 12V, OUTEN = 0, VID0, VID1, VID2, VID3 Floating Figure 4 (Note 6) (Note 6) VIMAX = VCC VSS = 0V, VIMAX = 0V, VIFB = VCC VSENSE = VOUT, VIMAX = VCC, VIFB = 0V (Notes 7, 8) VSENSE = 0V, VIMAX = VCC, VIFB = 0V VSENSE = 0V, VIMAX = 4V, VIFB from 5V VSENSE from 0V to Rated VOUT VSENSE from Rated VOUT to 0V VSENSE from Rated VOUT to VCC Figure 3, OUTEN, VID0, VID1, VID2, VID3 = 0 (Note 9) Figure 3, OUTEN, VID0, VID1, VID2, VID3 = 0 (Note 9)
1.265
q
-3
q q q q q
3 -7 12
7 -3 18 1500 300
q q
270 0.75
330 1.45
q q q q q q q q
90 40 120 210 60 60 20 1.9
170 120 230 400 140 140 60 2.1
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LTC1552
ELECTRICAL CHARACTERISTICS
SYMBOL VOTDD VSHDN tR, tF tNOL DCMAX VIH VIL R IN ISINK PARAMETER Over Temperature Driver Disable Shutdown Diver Rise and Fall Time Driver Nonoverlap Time Maximum G1 Duty Cycle VID0, VID1, VID2, VID3 Input High Voltage VID0, VID1, VID2, VID3 Input Low Voltage VID0, VID1, VID2, VID3 Internal Pull-Up Digital Output Sink Current
VCC = 5V, PVCC = 12V, TA = 25C unless otherwise noted (Note 2).
MIN 1.6 0.8 30 82 2 TYP 1.7 1.2 90 100 85 MAX 1.8 1.55 140 90 UNITS V V ns ns % V V k mA
CONDITIONS Figure 3, OUTEN, VID0, VID1, VID2, VID3 = 0 (Note 9) Figure 3, OUTEN, VID0, VID1, VID2, VID3 = 0 (Note 9) Figure 4 Figure 4 Figure 4
q q q q q q q
0.8 5.6 10
The q denotes specifications which apply over the full operating temperature range. Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Note 2: All currents into device pins are positive; all currents out of the device pins are negative. All voltages are referenced to ground unless otherwise specified. Note 3: This parameter is guaranteed by correlation and is not tested directly. Note 4: OUTEN is internally pulled low if VID0, VID1, VID2, VID3 are floating. Due to the internal pull-up resistors, there will be an additional 1mA/pin if any of the VID0, VID1, VID2, VID3 pins are pulled low.
Note 5: Supply current in normal operation is dominated by the current needed to charge and discharge the external FET gates. This will vary with the LTC1552 operating frequency, supply voltage and the external FETs used. Note 6: The open loop DC gain and transconductance from the SENSE pin to COMP pin will be (GERR)(1.265/3.3) and (gmERR)(1.265/3.3) respectively. Note 7: The current limiting amplifier can sink but cannot source current. Under normal (not current limited) operation, the output current will be zero. Note 8: Under typical soft current limit, the net soft start discharge current will be 130A ISSIL + (-14A)(ISS) = 116A. The soft start sink-to-source current ratio is designed to be 13:1. Note 9: When VID0, VID1, VID2, VID3 are all high, OUTEN will be forced low internally. The OUTEN trip voltages are guaranteed for all other input codes.
PIN FUNCTIONS
G2 (Pin 1): Gate Drive for the Lower N-Channel MOSFET, Q2. This output will swing from PVCC to PGND. It will always be low when G1 is high or when the output is disabled. To prevent undershoot during a soft start cycle, G2 is held low until G1 first goes high. PVCC (Pin 2): Power Supply for G1 and G2. PVCC must be connected to a potential of at least VIN + VGS(ON)Q1. If VIN = 5V, PVCC can be generated using a simple charge pump connected to the switching node between Q1 and Q2 (see Figure 7), or it can be connected to an auxiliary 12V supply if one exists. For applications where VIN = 12V, PVCC can be generated using a 5V + 12V charge pump (see Figure 9). PGND (Pin 3): Power Ground. PGND should be connected to a low impedance ground plane in close proximity to the source of Q2. GND (Pin 4): Signal Ground. GND is connected to the low power internal circuitry and should be connected to the negative terminal of the output capacitor where it returns to the ground plane. PGND and GND should form a star connection right at this pin. VCC (Pin 5): Power Supply. Power for the internal low power circuitry. VCC should be wired separately from the drain of Q1 if they share the same supply. A 10F bypass capacitor is recommended from this pin to GND. SENSE (Pin 6): Output Voltage Pin. Connect to the positive terminal of the output capacitor. SENSE is a very sensitive pin; for optimum performance, it requires an external 0.1F capacitor from this pin to GND. IMAX (Pin 7): Current Limit Threshold. This is set by the voltage drop across an external resistor connected between the drain of Q1 and IMAX. There is a 185A internal pull-down at IMAX.
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LTC1552
PIN FUNCTIONS
IFB (Pin 8): Current Limit Sense Pin. Connect to the switching node between the source of Q1 and the drain of Q2. If IFB drops below IMAX when G1 is on, the LTC1552 will go into current limit. The current limit circuit can be disabled by floating IMAX and shorting IFB to VCC. For VIN = 12V, a 15V Zener diode from IFB to PGND is recommended to prevent the voltage spike at IFB from exceeding the maximum voltage rating. SS (Pin 9): Soft Start. Connect to an external capacitor to implement a soft start function. During moderate overload conditions, the soft start capacitor will be discharged slowly in order to reduce the duty cycle. In hard current limit, the soft start capacitor will be forced low immediately and the LTC1552 will rerun a complete soft start cycle. CSS must be selected such that during power-up the total surge current through Q1 will not exceed the current limit value. COMP (Pin 10): External Compensation. The COMP pin is connected directly to the output of the error amplifier and the input of the PWM comparator. An RC network is used at this node to compensate the feedback loop to provide optimum transient response. OT (Pin 11): Over Temperature Fault. OT is an open drain output and will be pulled low if OUTEN is less than 2V. If OUTEN = 0, OT pulls low. FAULT (Pin 12): Fault Condition. FAULT is an open drain output. If VOUT reaches 15% above the rated value, FAULT will go low and G1 and G2 will be disabled. Once triggered, the LTC1552 will remain in this state until the power supply is recycled or the OUTEN pin is toggled. If OUTEN = 0, FAULT floats. PWRGD (Pin 13): Open Drain Signal to Indicate Validity of Output Voltage. A high indicates that the output has settled to within 5% of the rated output for more than 300s. PWRGD will go low if the output is out of regulation for more than 100s. If OUTEN = 0, PWRGD pulls low. NC (Pin 14): No Internal Connection. This pin will be VID4 in a future version of the LTC1552 conforming to the Intel VRM 8.1 specification. VID0, VID1, VID2, VID3 (Pins 18, 17, 16, 15): Digital Voltage Select. TTL inputs used to set the regulated output voltage required by the processor (Table 3). There is an internal 5.6k pull-up at each pin. When all four VIDn pins are high or floating, the OUTEN pin is forced to GND internally and the chip will shut down. OUTEN (Pin 19): Output Enable. TTL input which enables the output voltage. The external MOSFET temperature can be monitored with an external thermistor as shown in Figure 13. When the OUTEN input voltage drops below 2V, OT trips. As OUTEN drops below 1.7V, the drivers are internally disabled to prevent the MOSFETs from heating further. If OUTEN is less than 1.2V for longer than 30s, the LTC1552 will enter shutdown mode. The internal oscillator can be synchronized to an external clock by applying the external clocking signal to the OUTEN pin. G1 (Pin 20): Gate Drive for the Upper N-Channel MOSFET, Q1. This output will swing from PVCC to PGND. It will always be low when G2 is high or the output is disabled.
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LTC1552
BLOCK DIAGRAM
115% VREF
OUTEN
COMP I1 QSS
SS
MSD IFB VID2 VID3 IMAX I2 MHCL HCL MONO LVC
gm
CC
TEST CIRCUITS
VCC = 5V 10F 0.1F VCC PVCC PVCC = 12V 0.1F 10F IFB G1 FAULT OT 100pF VID0 TO VID3 VIDO TO VID3 SS 0.01F GND PGND SENSE 0.1F
LTC1552 * F02
3k 3k 3k 100pF 100pF
OUTEN PWRGD
LTC1552
C1 100pF
COMP RC 20k CC 0.01F
Figure 2
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+
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+
FC FAULT OT DISDR LOGIC PD PVCC DELAY PWRGD
-
-
PWM G1
+
G2 PGND REF ERR MIN MAX
+
-
-
+
-
+
FB
VREF DAC
SENSE VID0 VID1
VREF
VREF - 5%
VREF + 5%
+ -
50% VREF
1552 * BLOCK DIAGRAM
VIN = 5V
IN + 990F
C
3x 330F
Q1A, Q1B 2 IN PARALLEL NC VOUT LO 2H Q2 18A
IMAX
+
G2
CO 2310F 7x 330F
Q1A, Q1B, Q2: MOTOROLA MTD20N03HDL
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LTC1552
TEST CIRCUITS
VCC 0.1F PVCC 10F PVCC 0.1F 10F 10F VCC = 5V 0.1F PVCC = 12V 0.1F 10F tR VCC IFB LTC1552 G1 IMAX G2 SS NC GND PGND SENSE
LTC1552 * F03 LTC1552 * F04
VCC
VID0 VID1 VID2 VID3 VID0 VID1 VID2 VID3 VCC IFB OUTEN
tF 90% 90% 50% 50% 10% 10%
PVCC G1 LTC1552
G1 RISE/FALL 7500pF t NOL G2 RISE/FALL 7500pF
NC NC NC NC
PWRGD FAULT OT COMP
NC NC NC
SENSE GND PGND
G2
50%
50%
Figure 3
Figure 4
FUNCTION TABLES
Table 1. OT Logic
INPUT OUTEN (V) <2 >2 OUTPUT OT* 0 1 VID3 1 1 1 OUTPUT* VSENSE** X < 95% >95%/< 105% > 105% >115% OT 0 1 1 1 1 FAULT 1 1 1 1 0 PWRGD 0 0 1 0 0 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0
Table 2. PWRGD and FAULT Logic
INPUT OUTEN 0 1 1 1 1
* With external pull-up resistor. ** With respect to the rated output voltage. X Don't care.
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Table 3. Rated Output Voltage
INPUT PIN VID2 VID1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 VID0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 RATED OUTPUT VOLTAGE (V) SHUTDOWN 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5
LTC1552
APPLICATIONS INFORMATION
OVERVIEW The LTC1552 is a voltage feedback synchronous switching regulator controller (see Block Diagram) designed for use in high power, low voltage step-down (buck) converters. It is designed to satisfy the requirements of the Intel Pentium Pro power supply specification. It includes an onchip DAC to control the output voltage, a PWM generator, a precision reference trimmed to 1%, two high power MOSFET gate drivers and all the necessary feedback and control circuitry to form a complete switching regulator circuit. The LTC1552 includes a current limit sensing circuit that uses the upper external power MOSFET as a current sensing element, eliminating the need for an external sense resistor. Once the current comparator, CC, detects an over-current condition, the duty cycle is reduced by discharging the soft start capacitor through a voltage controlled current source. Under severe overloads or output short-circuit conditions, the chip will be repeatedly forced into soft start until the short is removed, preventing the external components from being damaged. Under output overvoltage conditions, the MOSFET drivers will be disabled permanently until the chip power supply is recycled or the OUTEN pin is toggled. OUTEN can optionally be connected to an external negative temperature coefficient (NTC) thermistor placed near the external MOSFETs or the microprocessor. Three threshold levels are internally provided to prevent the external circuitry from overheating. When OUTEN drops to 2V, OT will trip, issuing a warning to the external CPU. If the temperature continues to rise and the OUTEN input drops to 1.7V, the G1 and G2 pins will be disabled. Once OUTEN goes below 1.2V, the LTC1552 will go into shutdown mode, cutting the supply current to a minimum. If thermal shutdown is not required, OUTEN can be connected to a conventional TTL enable signal. The free running 300kHz PWM frequency can be synchronized to a faster external clock connected to OUTEN. Adjusting the oscillator frequency can add flexibility in the external component selection. See the Clock Synchronization section. Output regulation can be monitored with the PWRGD pin which in turn monitors the internal MIN and MAX comparators. If the output is 5% beyond the rated value for more than 100s, the PWRGD output will be pulled low. Once the output has settled within 5% of the rated value for more than 300s, PWRGD will return high. THEORY OF OPERATION Primary Feedback Loop The LTC1552 senses the output voltage of the circuit at the output capacitor with the SENSE pin and feeds this voltage back to the internal transconductance error amplifier ERR. ERR compares the resistor-divided output voltage FB to the 1.265V reference and passes an error signal to the PWM comparator. A pulse width modulated signal is generated by comparing this error signal with a fixed frequency sawtooth waveform generated by the oscillator. This PWM signal controls the external MOSFETs through G1 and G2, closing the loop. Loop compensation is achieved with an external compensation network at the COMP pin, which is connected to the output node of the ERR transconductance amplifier. MIN, MAX Feedback Loops Two additional comparators in the feedback loop provide high speed fault correction in situations where the ERR amplifier may not respond quickly enough. MIN compares the feedback signal FB to a voltage 60mV (5%) below the internal reference. If FB is lower than the threshold of this comparator, the MIN comparator overrides the ERR amplifier and forces the loop to full duty cycle, set by the internal oscillator at about 90%. Similarly, the MAX comparator forces the output to 0% duty cycle if FB is more than 5% above the internal reference. To prevent these two comparators from triggering due to noise, the MIN and MAX comparators' response times are deliberately controlled so that they take two or three cycles to respond. These two comparators help prevent extreme output perturbations with fast output transients, while allowing the main feedback loop to be optimally compensated for stability. Soft Start and Current Limit The LTC1552 includes a soft start circuit which is used for initial start-up and during current limit operation. The SS pin requires an external capacitor to GND, with the value determined by the required soft start time. An internal 14A current source is included to charge the external SS
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LTC1552
APPLICATIONS INFORMATION
capacitor. During start-up, the COMP pin is clamped to a diode drop above the voltage at the soft start pin. This prevents the error amplifier, ERR, from forcing the loop to maximum duty cycle. The LTC1552 will begin to operate at low duty cycle as the SS pin rises above about 1.2V (VCOMP = 1.8V). As SS continues to rise, QSS turns off and the error amplifier begins to regulate the output. The MIN comparator is disabled when soft start is active to prevent it from overriding the soft start function. The LTC1552 includes yet another feedback loop to control operation in current limit. Just before every falling edge of G1, the current comparator, CC, samples-andholds the voltage drop measured across the external MOSFET Q1 at the IFB pin. Note that when VIN = 12V, the IFB pin requires an external Zener to PGND to prevent voltage transients at the switching node between Q1 and Q2 from damaging internal structures. CC compares the voltage at IFB to the voltage at the IMAX pin. As the peak current rises, the measured voltage across Q1 increases, due to the drop across the RDS(ON) of Q1. When the voltage at IFB drops below IMAX, indicating that Q1's drain current has exceeded the maximum level, CC starts to pull current out of the external soft start capacitor, cutting the duty cycle and controlling the output current level. The CC comparator pulls current out of the SS pin in proportion to the voltage difference between IFB and IMAX. Under minor overload conditions, the SS pin will fall gradually, creating a time delay before current limit takes effect. Very short, mild overloads may not affect the output voltage at all. More significant overload conditions will allow the SS pin to reach a steady state and the output will remain at a reduced voltage until the overload is removed. Serious overloads will generate a large overdrive at CC, allowing it to pull SS down quickly and preventing damage to the output components. By using the RDS(ON) of Q1 to measure the output current, the current limiting circuit eliminates the sense resistor that would otherwise be required. This helps minimize the number of components in the high current path. Note that the current limit circuitry is not designed to be highly accurate; it is meant to prevent damage to the power supply circuitry during fault conditions. The exact current level where the limiting circuit begins to take effect will vary from unit to unit as the RDS(ON) of Q1 varies. For a given current limit level, the external resistor from IMAX to VIN can be determined by:
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RIMAX =
where:
(ILMAX )(RDS(ON)Q1)
IIMAX
I ILMAX = ILOAD + RIPPLE 2 ILOAD = maximum load current IRIPPLE = inductor ripple current =
(VIN - VOUT )(VOUT ) ( fOSC)(LO)(VIN)
fOSC = LTC1552 oscillator frequency = 300kHz LO = inductor value RDS(ON)Q1 = on resistance of Q1 at ILMAX IIMAX = internal 185A sink current at IMAX
VIN CIN
RIMAX
+
CC 185A IMAX G1 Q1 LO VOUT CO
-
IFB G2 LTC1552
1552 * F05
Q2
Figure 5. Current Limit Setting
OUTEN and Thermistor Input The LTC1552 includes a low power shutdown mode, controlled by the logic at the OUTEN pin. A high at OUTEN allows the part to operate normally. A low level at OUTEN stops all internal switching, pulls COMP and SS to ground internally and turns Q1 and Q2 off; OT and PWRGD are pulled low, and FAULT is left floating. In shutdown, the LTC1552 quiescent current will drop to about 150A; this remaining current is used to keep the thermistor sensing circuit at OUTEN alive. Note that the leakage current of the external MOSFETs may add to the total shutdown current consumed by the circuit, especially at elevated temperature.
LTC1552
APPLICATIONS INFORMATION
OUTEN is designed with multiple thresholds to allow it to also be utilized for over temperature protection. The power MOSFET operating temperature can be monitored with an external negative temperature coefficient (NTC) thermistor mounted next to the external MOSFET which is expected to run the hottest-usually the high side device, Q1. Electrically, the thermistor should form a voltage divider with another resistor, R1, connected to VCC. Their midpoint should be connected to OUTEN (see Figure 6). As the temperature increases, the OUTEN pin voltage is reduced. Under normal operating conditions, the OUTEN pin should stay above 2V. All circuits will function normally, and OT will remain in a high state. If the temperature gets abnormally high, the OUTEN pin voltage will eventually drop below 2V. OT will switch to a logic low, providing an overtemperature warning to the system. As OUTEN drops below 1.7V, the LTC1552 disables both FET drivers. This shuts the FET driver supply down, preventing any further heating. If OUTEN is less than 1.2V, the LTC1552 will enter shutdown mode. To activate any of these three modes, the OUTEN voltage must drop below the respective threshold for longer than 30s.
VCC 5.6k PENTIUM PRO SYSTEM VCC LTC1552 R1 R2 NTC THERMISTOR OUTEN G2 Q2 CO OT Q1 G1 LO VOUT VIN
Figure 6. OUTEN Pin as a Thermistor Input
Clock Synchronization
Q1
The internal oscillator can be synchronized to an external clock by applying the external clocking signal to the OUTEN pin. The synchronizing range extends from the internal 300kHz operating frequency up to 500kHz. If the external frequency is much higher than the natural free running frequency, the peak-to-peak sawtooth amplitude
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within the LTC1552 will decrease. Since the loop gain is inversely proportional to the amplitude of the sawtooth, the compensation network may need to be adjusted slightly. Note that the temperature sensing circuitry does not operate when external synchronization is used. MOSFET Gate Drive Power for the internal MOSFET drivers is supplied by PVCC. This supply must be above the input supply voltage by at least one power MOSFET VGS(ON) for efficient operation. This higher voltage can be supplied with a separate supply, or it can be generated using a simple charge pump as shown in Figure 7. The 90% maximum duty cycle ensures sufficient off-time to refresh the charge pump during each cycle. Figure 8 shows a tripling charge pump, which provides additional VGS overdrive to the external MOSFETs. This circuit can be useful for standard threshold MOSFETs which demand a higher turn-on voltage. An 18V Zener diode (1N5248B) is recommended with tripler charge pump designs to ensure that PVCC never exceeds the LTC1552's 20V absolute maximum PVCC voltage. This becomes more critical as VIN rises. With VIN = 12V, the doubler circuit of Figure 7 will also exceed the 20V limit. Figure 9 shows an alternate 17V charge pump derived from both the 5V and 12V supplies. Upon power down, G1 and G2 will both be held low to prevent output voltage undershoot. On power-up or wakeup from thermal shutdown, the drivers are designed such that G2 will be held low until G1 first goes high.
OPTIONAL FOR VIN > 5V VIN 1N5817 CIN PVCC 0.1F
LTC1552 * F06
1N5248B 18V
G1
LO VOUT Q2 CO
G2 LTC1552
1552 * F07
Figure 7. Doubling Charge Pump
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LTC1552
APPLICATIONS INFORMATION
VIN 1N5248B 18V PVCC 1N5817 0.1F 1N5817 1N5817
+
10F
0.1F
Q1 G1 LO VOUT Q2 G2 LTC1552
1552 * F08
Figure 8. Tripling Charge Pump
VCC = 5V 1N5817 10 VCC 1N5248B 18V PVCC 0.1F
VIN = 12V
CVCC
Q1 G1 Q2 G2 LTC1552
1552 * F09
LO VOUT CO
Figure 9. 17V Charge Pump for VIN = 12V
Power MOSFETs Two N-channel power MOSFETs are required for most LTC1552 circuits. They should be selected based primarily on threshold and on-resistance considerations. Thermal dissipation is often a secondary concern in high efficiency designs. The required MOSFET threshold should be determined based on the available power supply voltages and/ or the complexity of the gate drive charge pump scheme. In 5V input designs where a 12V supply is used to power PVCC, standard MOSFETs with RDS(ON) specified at VGS = 5V or 6V can be used with good results. The current drawn from the 12V supply varies with the MOSFETs used and the LTC1552 operating frequency, but is generally less than 50mA. LTC1552 designs that use a 5V VIN voltage and a doubler charge pump to generate PVCC will not provide enough drive voltage to fully enhance standard power MOSFETs.
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CIN
CO
Under this condition, the effective MOSFET RDS(ON) may be quite high, raising the dissipation in the FETs and reducing efficiency. Logic level FETs are a better choice for 5V -only systems or 12V input systems using the 17V charge pump of Figure 9. They can be fully enhanced with the generated charge pump voltage and will operate at maximum efficiency. Note that doubler charge pump designs running from supplies higher than 5V, and all tripler charge pump designs, should include a Zener clamp diode at PVCC to prevent transients from exceeding the absolute maximum rating at that pin. See the MOSFET Gate Drive section for more charge pump information. Once the threshold voltage has been selected, RDS(ON) should be chosen based on input and output voltage, allowable power dissipation and maximum required output current. In a typical LTC1552 buck converter circuit operating in continuous mode, the average inductor current is equal to the output load current. This current is always flowing through either Q1 or Q2 with the power dissipation split up according to the duty cycle: V DC (Q1) = OUT VIN V V -V DC (Q 2) = 1 - OUT = IN OUT VIN VIN The RDS(ON) required for a given conduction loss can now be calculated by rearranging the relation P = I2R.
RDS(ON) (Q1) = = PMAX(Q1)
CIN
(VIN )[PMAX (Q1)] (VOUT )(IMAX 2 ) PMAX(Q 2) RDS(ON) (Q 2) = [DC (Q 2)](IMAX 2 ) (VIN )[PMAX (Q 2)] = (VIN - VOUT )(IMAX2 )
[DC (Q1)](IMAX2 )
LTC1552
APPLICATIONS INFORMATION
PMAX should be calculated based primarily on required efficiency. A typical high efficiency circuit designed for Pentium Pro with a 5V input and 3.1V, 11.2A output might allow no more than 3% efficiency loss at full load for each MOSFET. Assuming roughly 90% overall efficiency at this current level, this gives a PMAX value of [(3.1 * 11.2A/ 0.9)(0.03)] = 1.16W per FET and a required RDS(ON) of:
(5V)(1.16W) = 0.015 (3.1V)(11.2A2 ) (5V)(1.16W) = 0.024 RDS(ON) (Q 2) = (5V - 3.1V)(11.2A2 )
RDS(ON) (Q 1) =
Note that the required RDS(ON) for Q2 is roughly twice that of Q1 in this example. This application might specify a single 0.024 device for Q2 and parallel two more of the same devices to form Q1. Note also that while the required RDS(ON) values suggest large MOSFETs, the dissipation numbers are only 1.16W per device or less -- large TO-220 packages and heat sinks are not necessarily required in high efficiency applications. Siliconix Si4410DY or International Rectifier IRF7413 (both in SO-8) or Siliconix SUD50N03 or Motorola MTD20N03HDL (both in DPAK) are small footprint surface mount devices with RDS(ON) values below 0.03 at 5V of gate drive that work well in LTC1552 circuits. Note that using a higher PMAX value in the RDS(ON) calculations will generally decrease MOSFET cost and circuit efficiency and increase MOSFET heat sink requirements. Inductor Selection The inductor is often the largest component in the LTC1552 design and should be chosen carefully. Inductor value and type should be chosen based on output slew rate requirements and expected peak current. Inductor value is primarily controlled by the required current slew rate. The maximum rate of rise of current in the inductor is set by its value, the input-to-output voltage differential and the maximum duty cycle of the LTC1552. In a typical 5V input, 3.1V output application, the maximum rise time will be:
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(90%)
(VIN - VOUT )(Amps) = 1.71 A L s (L)(Second)
where L is the inductor value in H. With proper frequency compensation, the combination of the inductor and output capacitor will determine the transient recovery time. In general, a smaller value inductor will improve transient response at the expense of ripple and inductor core saturation rating. A 2H inductor would have a 0.86A/s rise time in this application, resulting in a 5.8s delay in responding to a 5A load current step. During this 5.8s, the difference between the inductor current and the output current must be made up by the output capacitor, causing a temporary voltage droop at the output. To minimize this effect, the inductor value should usually be in the 1H to 5H range for most typical 5V input LTC1552 circuits. Different combinations of input and output voltages and expected loads may require different values. Once the required value is known, the inductor core type can be chosen based on peak current and efficiency requirements. Peak current in the inductor will be equal to the maximum output load current plus half of the peak-topeak inductor ripple current. Ripple current is set by the inductor value, the input and output voltage and the operating frequency. If the efficiency is high, the ripple current is approximately equal to: IRIPPLE =
(VIN - VOUT )(VOUT ) ( fOSC)(LO )(VIN )
fOSC = LTC1552 oscillator frequency LO = inductor value Solving this equation with our typical 5V to 3.1V application with a 2H inductor, we get:
(1.9)(0.62) = 1.96A P -P (300kHz)(2H)
Peak inductor current at 11.2A load: 11.2A + 1.96A = 12.18A 2
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LTC1552
APPLICATIONS INFORMATION
The ripple current should generally be between 10% and 40% of the output current. The inductor must be able to withstand this peak current without saturating, and the copper resistance in the winding should be kept as low as possible to minimize resistive power loss. Note that in non-current-limited circuits, the current in the inductor may rise above this maximum under short-circuit or fault conditions; the inductor should be sized accordingly to withstand this additional current. Inductors with gradual saturation characteristics are often the best choice. Input and Output Capacitors A typical LTC1552 design puts significant demands on both the input and the output capacitors. During normal steady load operation, a buck converter like the LTC1552 draws square waves of current from the input supply at the switching frequency. The peak current value is equal to the output load current and the minimum value is near zero. Most of this current is supplied by the input bypass capacitor. The resulting RMS current flow in the input capacitor will heat it up, causing premature capacitor failure in extreme cases. Maximum RMS current occurs with 50% PWM duty cycle, giving an RMS current value equal to IOUT/2. A low ESR input capacitor with an adequate ripple current rating must be used to ensure reliable operation. Note that capacitor manufacturers' ripple current ratings are often based on only 2000 hours (three months) lifetime at rated temperature. Further derating of the input capacitor ripple current beyond the manufacturer's specification is recommended to extend the useful life of the circuit. The output capacitor in a buck converter sees much less ripple current under steady-state conditions than the input capacitor. Peak-to-peak current is equal to that in the inductor, usually 10% to 40% of the total load current. Output capacitor duty places a premium not on power dissipation but on ESR. During an output load transient, the output capacitor must supply all of the additional load current demanded by the load until the LTC1552 can adjust the inductor current to the new value. ESR in the output capacitor results in a step in the output voltage equal to the ESR value multiplied by the change in load current. An 11A load step with a 0.05 ESR output capacitor will result in a 550mV output voltage shift; this is 18% of the output voltage for a 3.1V supply! Because of the strong relationship between output capacitor ESR and output load transient response, the output capacitor is usually chosen for ESR, not for capacitance value; a capacitor with suitable ESR will usually have a larger capacitance value than is needed to control steady-state output ripple. Electrolytic capacitors rated for use in switching power supplies with specified ripple current ratings and ESR can be used effectively in LTC1552 applications. OS-CON electrolytic capacitors from Sanyo and other manufacturers give excellent performance and have a very high performance/size ratio for electrolytic capacitors. Surface mount applications can use either electrolytic or dry tantalum capacitors. Tantalum capacitors must be surge tested and specified for use in switching power supplies. Low cost, generic tantalums are know to have very short lives followed by explosive deaths in switching power supply applications. AVX TPS series surface mount devices are popular surge tested tantalum capacitors that work well in LTC1552 applications. A common way to lower ESR and raise ripple current capability is to parallel several capacitors. A typical LTC1552 application might exhibit 5A input ripple current. Sanyo OS-CON part number 10SA220M (220F/10V) capacitors feature 2.3A allowable ripple current at 85C; three in parallel at the input (to withstand the input ripple current) will meet the above requirements. Similarly, AVX TPSE337M006R0100 (330F/6V) have a rated maximum ESR of 100m; seven in parallel will lower the net output capacitor ESR to 14m. Feedback Loop Compensation The LTC1552 voltage feedback loop is compensated at the COMP pin, attached to the output node of the internal gm error amplifier. The feedback loop can generally be compensated properly with an RC + C network from COMP to GND as shown in Figure 10. Loop stability is affected by the inductor and output capacitor values and by other factors. Although a mathematical approach to frequency compensation can be used, the added complication of input and/or output
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LTC1552
APPLICATIONS INFORMATION
VID0, VID1, VID2, VID3, PWRGD AND FAULT
LTC1552 COMP
RC C1 CC
1554 * F10
Figure 10. Compensation Pin Hook-Up
filters, unknown capacitor ESR, and gross operating point changes with input voltage, load current variations and frequency of operation, all suggest a more practical empirical method. This can be done by injecting a transient current at the load and using an RC network box to iterate toward the final compensation values, or by obtaining the optimum loop response using a network analyzer to find the actual loop poles and zeros. Table 4 shows the suggested compensation components for 5V to 3.1V applications based on the inductor and output capacitor values. The values were calculated using multiple paralleled 330F AVX TPS series surface mount tantalum capacitors as the output capacitor. The optimum component values might deviate from the suggested values slightly because of board layout and operating condition differences.
Table 4. Suggested Compensation Network for 5V to 3.1V Application Using Multiple 330F AVX Output Capacitors
LO (H) 1 1 1 1 2.7 2.7 2.7 2.7 5.6 5.6 5.6 5.6 CO(F) 990 1980 4950 9900 990 1980 4950 9900 990 1980 4950 9900 RC(k) 2.7 5.1 15 27 5.1 10 27 51 15 27 68 150 CC(F) 0.01 0.0047 0.0018 0.001 0.0047 0.0022 0.001 470pF 0.0018 0.001 330pF 180pF C1 (pF) 330 180 68 39 180 100 39 18 68 33 15 10
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The digital inputs (VID0, VID1, VID2, VID3) program the internal DAC which in turn controls the output voltage. These digital input controls are intended to be static and are not designed for high speed switching. Forcing VOUT to step from a high to a low voltage suddenly by changing the VIDn pins quickly can cause FAULT to trip. Figure 11 shows the relationship between the VOUT voltage, PWRGD and FAULT. To prevent PWRGD from interrupting the CPU unnecessarily, the LTC1552 has a built in tPWRBAD delay to prevent noise at the SENSE pin from toggling PWRGD. The internal time delay is designed to take about 100s for PWRGD to go low and 300s for it to recover. Once PWRGD goes low, the internal circuitry watches for the output voltage to exceed 115% of the rated voltage. If this happens, FAULT will be triggered. Once FAULT is triggered, G1 and G2 will be forced low immediately and the LTC1552 will remain in this state until VCC power supply is recycled or OUTEN is toggled.
15% VOUT 5% RATED VOUT -5% t PWRBAD PWRGD t PWRGD t FAULT
FAULT
1552 * F11
Figure 11. PWRGD and FAULT
LAYOUT CONSIDERATIONS When laying out the printed circuit board, the following checklist should be used to ensure proper operation of the LTC1552. These items are also illustrated graphically in the layout diagram of Figure 12. The thicker lines show the high current paths. Note that at 10A current levels or above, current density in the PC board itself is a serious concern. Traces carrying high current should be as wide as possible. For example, a PCB fabricated with 2oz. copper requires a minimum trace width of 0.15" to carry 10A.
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LTC1552
APPLICATIONS INFORMATION
1. The signal and power grounds should be segregated. The LTC1552 signal ground must return to the (-) plate of the output capacitor, the negative terminal of SS and the COMP RC network. The power ground should return to the source of the lower MOSFET and the (-) plate of the CIN and the lead lengths should be as short as possible. The power ground and signal ground should be brought together at only one point, right at the LTC1552 GND and PGND pins. This helps to minimize internal ground disturbances in the LTC1552 and prevents differences in ground potential from disrupting internal circuit operation. 2. The VCC and PVCC decoupling capacitors should be as close to the LTC1552 as possible. The 10F bypass capacitors shown at VCC and PVCC will help provide optimum regulation performance. 3. The (+) plate of CIN should be connected as close as possible to the drain of the upper MOSFET. An additional 1F ceramic capacitor between VIN and power ground is recommended. 4. The SENSE pin is very sensitive to pickup from the switching node. Care should be taken to isolate SENSE from possible capacitive coupling to the inductor switching signal. A 0.1F is required between the SENSE pin and the GND pin next to the LTC1552. 5. OUTEN is a high impedance input and should be externally pulled up to a logic HIGH for normal operation.
VIN
+
CIN VOUT LO Q2 PVCC 1 2 10F 0.1F 3 G2 PVCC G1 OUTEN 20 19 Q1
+
CO
+
10F
BOLD LINES INDICATE HIGH CURRENT PATHS CSS C1
Figure 12. LTC1552 Layout Diagram
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PGND
VID0
18
VID0
5.6k 5.6k 5.6k
4 0.1F 0.1F 5 6 RIMAX 7 8 9 10 RC CC
GND
LTC1552
VID1
17
VID1
VCC SENSE IMAX IFB SS COMP
VID2 VID3 NC PWRGD FAULT OT
16 15 14 13 12 11
VID2 VID3 NC
1552 * F12
LTC1552
TYPICAL APPLICATION
VIN = 5V 5.6k 5.6k PWRGD PWRGND FAULT PENTIUM PRO SYSTEM OT VID0 TO VID3 OUTEN 5V 1.8k DALE NTHS-1206N02 COMP RC 20k CC 0.01F SS CSS 0.01F GND PGND G2 SENSE 0.1F Q2 LTC1552 VCC IMAX PVCC G1 0.1F 0.1F 10F 1.6k 1N5817
IN + 990F
5.6k
C1 100pF
Figure 13. Single Supply 5V to 2.1V to 3.5V Application with Thermal Monitor
PACKAGE DESCRIPTION
0.205 - 0.212** (5.20 - 5.38)
0.005 - 0.009 (0.13 - 0.22)
0.022 - 0.037 (0.55 - 0.95)
*DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE **DIMENSIONS DO NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
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3x 330F
Q1A, Q1B 2 IN PARALLEL LO 2H/18A
IFB
O + 2310F
C
VOUT
7x 330F
LTC1552 * F13
Q1A, Q1B, Q2 = MOTOROLA MTD20N03HDL
Dimensions in inches (millimeters) unless otherwise noted. G Package 20-Lead Plastic SSOP (0.209)
(LTC DWG # 05-08-1640)
0.278 - 0.289* (7.07 - 7.33) 20 19 18 17 16 15 14 13 12 11
0.301 - 0.311 (7.65 - 7.90)
1 2 3 4 5 6 7 8 9 10 0.068 - 0.078 (1.73 - 1.99)
0 - 8
0.0256 (0.65) BSC
0.010 - 0.015 (0.25 - 0.38)
0.002 - 0.008 (0.05 - 0.21)
G20 SSOP 0595
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LTC1552
TYPICAL APPLICATION
10 10F 5.6k 5.6k PWRGD PWRGND FAULT PENTIUM PRO SYSTEM NC OT LTC1552 VID0 TO VID3 OUTEN COMP RC 20k CC 0.01F SS CSS 0.01F GND PGND G2 SENSE 0.1F Q1, Q2 = MOTOROLA MTD20N03HDL IFB 1N5245B 15V LO 2H Q2 18A
O + 2310F
C1 100pF
RELATED PARTS
PART NUMBER LTC1142 LTC1148 LTC1149 LTC1159 LTC1266 LTC1430 LTC1435 LTC1438 DESCRIPTION Current Mode Step-Down Switching Regulator Controller Current Mode Step-Down Switching Regulator Controller Current Mode Step-Down Switching Regulator Controller Current Mode Step-Up/-Down Switching Regulator Controller High Power Step-Down Switching Regulator Controller High Efficiency Low Noise Synchronous Stepdown Switching Regulator Dual High Efficiency Low Noise Synchronous Stepdown Switching Regulator COMMENTS Synchronous, VIN 20V Synchronous, VIN 48V, for Standard Threshold FETs Synchronous, VIN 40V, for Logic Threshold FETs Synchronous N- or P-Channel FETs, Comparator/Low-Battery Detector Synchronous N-Channel FETs, Voltage Mode Drive Synchronous N-Channel, VIN 36V Dual LTC1435 with Power-On Reset Current Mode Dual Step-Down Switching Regulator Controller Dual Version of LTC1148
16
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 q FAX: (408) 434-0507 q TELEX: 499-3977
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VCC = 5V VIN = 12V 1N5817 1N5248B 18V 1.6k 0.1F Q1
IN + 940F
0.1F
C
VCC
PVCC
IMAX G1
2x 470F SANYO OS-CON
C
VOUT
7x 330F
LTC1552 * F14
Figure 14. Synchronized 12V to 3.5V Application
LT/HP 0996 162 * PRINTED IN USA
(c) LINEAR TECHNOLOGY CORPORATION 1996

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